This invention relates to a device for generating a logical address in response to an instruction word or instruction which specifies first through third words.
In the manner known in the art of electronic digital computers, a logical address is generated from an instruction word. An electronic digital computer comprises an executing unit, such as an arithmetic unit, a plurality of base registers, and a plurality of index registers. The instruction word comprises an operation code field, a base register field, an index register field, and an offset field. The operation code field indicates an operation which should be carried out by the executing unit. The base register field specifies one of the base registers that indicates a first word for use in generating a logical address. The index register field specifies one of the index registers that indicates a second word for use in generating the logical address. The offset field indicates an offset for use in generating the logical address. In relation to the first and the second words, the offset is herein called a third word. It is therefore possible to understand that an instruction word specifies the first through the third words.
Conventionally, each of the first through the third words has a predetermined word length which may be called a single word length. On the other hand, it is a recent trend to widen a memory space of the computer in order to cope with a much increased amount of data which the computer should process. The memory space is widened by typically using the first and the second words, each having either a double word length or a longer word length. In this event, a conventional logical address generating device must comprise an adder and a carry look ahead, each for the double or the longer word length. In other words, the conventional logical address generating device must have an increased amount of hardware. In addition, it takes twice as long a time according to a simple-minded estimation to generate the logical address when the first and the second words are of the double word length. The time may be shortened by using a high-speed carry look ahead. Even with the high-speed carry look ahead, it is very difficult to generate the logical address in one machine cycle.